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- Especially, the quality of gate dielectric layer determines the reliability and electrical performance of ultra large scale integrated (ULSI) circuit. 特別是閘極介電層的品質(zhì)能決定ULSI電路的穩定度與電特性表現。
- We focus on how the processes in repaid thermal processor (RTP) affect the electrical characteristics quality of gate dielectric layer. 我們將會(huì )集中以快速熱制程如何影響介電層電特性。
- Tunneling allows voltage to flow from the control gate to the floating gate through the dielectric layer of oxide which separates them. 允許從隧道流電壓控制的浮動(dòng)柵柵絕緣層氧化物通過(guò)分隔他們。
- NTBI induced device degradation can be suppressed by a SiN capping layer between Poly-Si gate and high k dielectric layer. 在閘極與高介電常數介電層間使用氮化矽可有效抑制負偏壓溫度不穩定性的現象。
- Results show that HfO 2 gate dielectric hold good electrical characteristics. 實(shí)驗結果顯示 :Hf O2 柵介質(zhì)電容具有良好的 C-V特性 ,較低的漏電流和較高的擊穿電壓。
- Ultra-thin Si 3N 4/SiO 2(N/O) stack gate dielectric with EOT of 2.1nm is fabricated successfully,and its characteristics are investigated. 成功制備了EOT(equivalentoxidethickness)為 2 1nm的Si3 N4/SiO2 (N/O)stack柵介質(zhì) ;并對其性質(zhì)進(jìn)行了研究 .
- The reliability of strain silicon,gate dielectric and copper interconnection are discussed,and some new researches are presented. 簡(jiǎn)介了應變硅材料、柵介質(zhì)的工藝及銅互連的可靠性,并對新的研究方向做了介紹。
- For continued technology scaling, high k materials are required to replace SiO_2 as gate dielectric in the next generation metal oxide field effect transistors (MOSFET). 在過(guò)去二十多年里,Si基元器件的大小遵循Moore定律按比例的持續減小。 對于下一代金屬氧化物半導體場(chǎng)效應管(MOSFET)器件,原來(lái)的柵極介電材料SiO_2已經(jīng)不再適合使用。
- When an inhomogeneous plane wave is introduced into a dense dielectric layer, it can bounce between the two boundaries. 把一非均勻平面波引進(jìn)折射率較高的介質(zhì)層時(shí)，它會(huì )在上下界面間來(lái)回地“彈”射。
- Dual damascene technology of Cu / low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介紹了銅/低介電常數介電層的雙嵌入式工藝,該工藝已大規模應用于動(dòng)態(tài)記憶存儲器(DRAM)和邏輯電路器件中。
- By complementing the equivalent oxide thickness (EOT) of a 1.7nm nitride/oxynitride (N/O) stack gate dielectric (EOT=1.7nm) with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. 在國內首次將等效氧化層厚度為1·7nm的N/O疊層柵介質(zhì)技術(shù)與W/Ti N金屬柵電極技術(shù)結合起來(lái);用于柵長(cháng)為亞100nm的金屬柵CMOS器件的制備.
- And the conclusion is presented too.It is easy to design and manufacture waveguide filter using dielectric layer PBG structures. 利用介質(zhì)層PBG結構來(lái)制作波導濾波器具有設計簡(jiǎn)單、易于實(shí)現的顯著(zhù)優(yōu)點(diǎn)。
- As reducing the gate length toward to submicron CMOS device, selecting a gate dielectric material to improve the electric characteristics and been demonstrated by using ISE-TCAD simulation tool. 從改變氧化層材料與線(xiàn)寬之方式對元件性能的提升并藉由ISE-TCAD 模擬工具來(lái)探討。
- Silicon oxide has been used as a gate dielectric of MOSFETs for more than forty years since MOSFET had been introduced due to its excellent stability, uniformity, and easy fabrication process. 自從金氧半導體場(chǎng)效電晶體被發(fā)明以來(lái)，二氧化矽巳經(jīng)被用作為其閘極氧化層超過(guò)四十年之久，因為二氧化矽擁有極佳的穩定性和均勻度且制作過(guò)程較為簡(jiǎn)單。
- We show the reflection and transmission behaviors when SPPs propagate along the metallic surface with one dimensional dielectric layer coated. 我們進(jìn)一步討論了表面等離子體激元在一維結構正入射時(shí)的反射性質(zhì)，以及完全帶隙的構造，和初步的實(shí)驗結果。
- While the top electrode is located on the third dielectric layer, in which each third dielectric layer and its top electrode compose a stack structure. 而上電極是位于第三介電層上，其中由每一第三介電層與其上的上電極組成一個(gè)堆棧結構。
- Dual damascene technology of Cu/ low dielectric layer is introduced in this paper, andthis technology has been used in manufacturing DRAM and logic devices. 介紹了銅/介電常數介電層的雙嵌入式工藝,該工藝已大規模應用于動(dòng)態(tài)記憶存儲器(RAM)邏輯電路器件中。
- DPN process for MOS gate dielectric treatment 絕緣柵氮處理技術(shù)
- nitride/oxynitride gate dielectric stack 氮氧疊層柵介質(zhì)
- As a vertically extended contact surface is formed between the said metallic pad and the dielectric layer in the dentritic structure, the contact surface and adhesion are increased. 由于在金屬接線(xiàn)墊層及位于樹(shù)枝狀子結構中的介電層之間形成垂直延伸接觸表面，因此擴大了接觸面積而增強附著(zhù)力；樹(shù)枝狀子結構在介電層的邊緣部分不連續可有效截斷而防止形成裂縫。
