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- This change of capacitance value can be detected by TS. TS可以探測到電容量的這種變化。
- Are there any precautions when adjusting the capacitance value? 調整電容值時(shí)有哪些注意事項?
- One should take the parasitic capacitance into account wherever one is making an overlap with metal layers or wells. 有覆蓋金屬層或阱區時(shí),須考慮寄生電容。
- Measure capacitance value in Farad unit by RC time constant operation. 用RC時(shí)間持續運轉來(lái)測量法拉單位的電容值。
- One should try to avoid running metal over poly gate. As this cause to increase in parasitic capacitance. 避免金屬在多晶硅柵上走線(xiàn),會(huì )增加寄生電容。
- Can you ship Trimmer Capacitors with the angle and capacitance value preset? 你們可以提供帶預設角和電容值的微調電容器嗎?
- It details the IC design process and VLSI circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays. 它詳細規定了集成電路設計過(guò)程和超大規模集成電路電路，包括門(mén)陣列，可編程邏輯器件和陣列，寄生電容，及輸電線(xiàn)路的延誤。
- The various applications and features are described of gate-source parasitic capacitance with synchronous rectifier diodes in the realization of actuating rectifier. 闡述了同步整流管的柵源寄生電容在實(shí)現整流器件驅動(dòng)中的不同應用及其特點(diǎn),并給出了應用實(shí)例分析。
- First, the capacitor inserted allows a low frequency "extension" due to the resonance between the transformers inductance and the capacitance value. 第一，耦合電容和變壓器初級電感之間的諧振可以容許更好的低頻延展。
- Which Trimmer Capacitors have small minimum capacitance values? 哪種微調電容器有最小電容值?
- Likewise , C1 must have a large capacitance value is order to provide operating current for the load when D1 and D2 are not conducting. 同樣，C1容量必須足夠大，才可以保證在D1和D2不導通期間為負載提供運行電流。如果C1容量太小。
- Due to the introduced PN junction, the photocurrent is made up by both electronic and pole.As a result, the sensitivity and signal to noise ratio are increased, the parasitic capacitance is decreased. 由于引入PN注入結，新型光電器件溝道電流同時(shí)存在電子電流和空穴電流，提高了器件的響應靈敏度，避免了大的寄生電容，提高了信噪比。
- A novel configuration of a MOS varactor is designed for good linearity of Kvco,as well as a new digital capacitor controlled array topology with lower parasitic capacitance and lower Ron. 通過(guò)改變MOS變容管的接入方法實(shí)現了更好的壓控增益線(xiàn)性度,并采用了新的低寄生電容、低導通電阻的數控電容陣列結構來(lái)補償工藝變化帶來(lái)的頻率變化。
- Silicon on insulator(SOI) structure, as a very large scale integrated circuit(VLSI) wafer, has attractive features such as radiation-hardening, no parasitic capacitance and latch-up effect. 絕緣體上生長(cháng)的薄單晶硅膜(SOI)具有良好的橫向絕緣、抗輻照、無(wú)鎖存效應和無(wú)寄生電容，并能有效地提高硅集成電路的速度和集成度，在深亞微米VLSI技術(shù)中，具有很大的優(yōu)勢和潛力。
- The impacts of these parasitic capacitances on interface circuit are analyzed. 建立了某種硅微機械陀螺儀的電路模型,分析了寄生電容對接口電路的影響。
- In the measurement process, the 66 capacitance values from ECT sensor are the input of the voidage model, and the output of the model is the voidage value. 運用該方法測量空隙率時(shí)，以ECT電容傳感器獲取的66個(gè)獨立電容值作為空隙率模型的輸入，計算即可得空隙率。
- The parasitic capacitances of IGBT and other distributed parameters would induce adverse effects to drive wave. 柵極驅動(dòng)電壓必須有足夠快的上升和下降速度。
- controllable parasitic capacitance 可控寄生電容
- At last,some methods,such as the adoption of SOI craftwork and reasonable disposal wires,are put forward to decrease the parasitic capacitances. 提出了采用新工藝和合理的布線(xiàn)方法減小與活動(dòng)結構間的電容，從而提高信噪比。
- In previous work a noncirculating type of bearing current caused by parasitic capacitive coupling from stator windings to the rotor was identified. 在早先的工作中一非循環(huán)類(lèi)型生由從固定子卷到轉子的寄生電容的聯(lián)結所引起的涌流被識別。
