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- The Processer Clock is the Master Clock. 請教高手：處理器時(shí)鐘，主機時(shí)鐘，外設時(shí)鐘的關(guān)系？
- Design and Realization of Embedded Synchronization Clock System. 嵌入式同步時(shí)鐘系統的設計與實(shí)現。
- Screening Tests on master clock culture medium of Agrocybe aegerita(Brig.)Sing. 楊樹(shù)菇母種培養基篩選試驗
- The level difference of these re-sults at SO is a main reflection of the level difference of UTC master clock. So結果的水平差異主要是協(xié)調世界時(shí)主鐘水平差異的反映；
- The normal idea to make up a digital controled oscillator (DCO)of the digital phase locked loop (DPLL)is to delete the pulses unwanted It need that the master clock frequency must be more faster than the output frepuency of the DPLL. 傳統的數字鎖相環(huán) (DPLL)多采用吞脈沖的方法來(lái)實(shí)現DCO ,此方法要求工作頻率遠高于DPLL的輸出頻率。
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock. Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主時(shí)鐘與PCM數據端時(shí)鐘或ADPCM數據端時(shí)鐘可以是異步的，不同的時(shí)鐘控制范圍內的數據同步或交換是通過(guò)一個(gè)深度為8的FIFO來(lái)實(shí)現的；
- The master clock can be asynchronous with PCM data side clock or ADPCM data side clock.Using an 8-depth async FIFO solves the synchronization and exchange of data be-tween different clock domains. 主時(shí)鐘與PCM數據端時(shí)鐘或ADPCM數據端時(shí)鐘可以是異步的，不同的時(shí)鐘控制范圍內的數據同步或交換是通過(guò)一個(gè)深度為8的FIFO來(lái)實(shí)現的；
- This essay mainly introduced electric time synchronous net-form mode,the basic concept and the determinant of GPS system.The basic technical need of substation GPS master clock is briefly summarized. 主要介紹了電力時(shí)間同步組網(wǎng)模式、GPS系統的基本概念及其決定因素,并對變電站GPS主時(shí)鐘的基本技術(shù)要求作了簡(jiǎn)短小結。
- Study of biological clock system in mammals 哺乳動(dòng)物的生物鐘系統研究
- satellite disciplined clock system 衛星馴服時(shí)鐘系統
- Support the HR Specialist to register the clocking system，such as attendance and overtime etc. Send the Statistics reports to HR manager and HR specialist . 協(xié)助人事專(zhuān)員進(jìn)行考勤系統登記，例如出勤和加班統計，將統計發(fā)送給人力資源經(jīng)理和人事專(zhuān)員。
- best master clock algorithm(BMC) 最佳主時(shí)鐘算法
- Best Master Clock (BMC) algorithm 最佳主時(shí)鐘算法
- master clock frequency of a computer 計算機主頻
- It has been found that the major limitations of typical 8-bit MCU are the ALU structure based on accumulator ,the clock system design and the CISC architecture adopted in MCS-51 design. 分析發(fā)現,在傳統八位微處理器設計中,影響其整體性能的主要原因是:基于累加器的ALU結構、CISC指令體系、時(shí)鐘系統設計以及系統構架。
- I suppose you also have a caste system in your society. 我想你們的社會(huì )里也有一種等級制度。
- The right to dissent is part of our political system. 有持異議的權利是我們政治體制的組成部分。
- The cruel master beat his slaves with a whip. 殘酷的主人鞭打他的奴隸。
- I didn't wake up until I heard the alarm clock. 直到聽(tīng)到鬧鐘的鈴聲我才醒來(lái)。
