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- gate level logic simulation 門(mén)級邏輯模擬
- After study a series array multipliers algorithms and architectures, . the author design a high-performance multiplier in logic gate level, which using Booth and Wallace skill. 本文研究討論了各種不同陣列乘法器的結構和原理,并完成了在門(mén)電路級設計了32位基4Booth編碼并采用42壓縮的Wallace高性能陣列乘法器電路。
- This thesis has accomplished the design of register transfer level (RTL) of every unit in the digital processing module, and passed function verification, logic synthesis, and gate level verification. 本文完成了數字處理模塊各個(gè)單元的寄存器傳輸級（RTL）設計，并通過(guò)了功能仿真、邏輯綜合與門(mén)級仿真。
- The verification includes RTL simulation, gate level simulation and static timing analysis. 驗證工作包括RTL級仿真、門(mén)級仿真和靜態(tài)時(shí)序分析。
- Based on the VRM,a simple RTL logic simulator was implemented for verification of the model. 基于該模型 ;還實(shí)現了一個(gè)簡(jiǎn)單的RTL邏輯模擬程序以驗證VRM模型的可行性 .
- Finally and some discussions are made on the advantages and disadvantages of the Gate Level Evolvable Hardware. 在函數級進(jìn)化中，首先在FPGA內部設計了用高級功能模塊和互連矩陣構成函數級進(jìn)化的結構，探討了如何利用這種結構縮短染色體編碼并設計了用于函數級進(jìn)化的系統平臺。
- The latter is implemented through comparing the two different results from Ski IA-64 hardware simulator and Verilog-XL logic simulator. 后者是通過(guò)比對同一測試碼在Ski IA-64硬件模擬器和Verilog-xL邏輯模擬下的不同運行結果實(shí)現的。
- Constant components and output opened ports in the result of high level synthesis lead to explicit redundancy in gate level technology mapping. 高級綜合結果中常量元件和輸出懸空端口導致門(mén)級工藝映射結果中存在顯式冗余。
- In order to improve the security of the system, the breakers are operated to control the power of the sluices in the dynamoelectric method and the gate level gauge is composed of absolute Gray coder and elastic equilibrium sensor. 為了提高系統的安全性 ,采用了電動(dòng)操作斷路器對閘門(mén)的動(dòng)力電源進(jìn)行控制。 閘位計采用絕對值格雷碼編碼器以及彈性平衡傳感器組成。
- The design, now, has passed the logic simulation successfully in Daisy computer workstation. 目前，線(xiàn)路級的設計已經(jīng)完成，并且成功地通過(guò)了Daisy工作站的計算機邏輯模擬。
- This flow could use the gated clock,the operand isolation and the gate level optimization to decrease the power consumption without changing the original design. 這種綜合流程在不改變原有電路設計的前提下同時(shí)采用了門(mén)控時(shí)鐘、操作數隔離和門(mén)級功率優(yōu)化來(lái)降低功耗。
- gate level combinational circuits [計] 門(mén)級組合電路
- Eseutil verifies the page level and Extensible Storage Engine (ESE) level logical integrity of the database but does not verify database integrity at the Information Store level. Eseutil可驗證頁(yè)級別和可擴展存儲引擎(ESE)級別的數據庫邏輯完整性,但不會(huì )驗證信息存儲級別的數據庫完整性。
- An expetr system is designed based on peculiarities of substation operation and by applying artificial intellesence theory and Principle of logic simulation. 本文根據變電運行的特點(diǎn)，應用人工智能和邏輯仿真的原理，給出了由模擬量和計算機系統組成的硬件系統方案。
- A man appeared at the castle gate in the guise of a woodcutter. 一個(gè)男子打扮成樵夫的模樣出現在城堡的門(mén)口。
- Did you remember to padlock the gate? 你是否記得用掛鎖把大門(mén)鎖上？
- I saw him make by the gate on his bicycle. 我看見(jiàn)他騎自行車(chē)從大門(mén)旁邊過(guò)去了。
- The truck came to a dead stop out of the gate. 那輛卡車(chē)在大門(mén)外突然停下。
- I can open the back gate at midnight. 午夜的時(shí)候我可以打開(kāi)后門(mén)。
- A flock of sheep poured through the gate. 一群羊從羊圈口涌了出來(lái)。
