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- The arrow diagram does not indicate critical path. 箭線(xiàn)圖表不注明主要的路徑。
- Critical path and critical activities: time management principles. 關(guān)鍵路徑與關(guān)鍵作業(yè)的權衡之道:時(shí)間管理法則。
- Explain the strengths and weaknesses of critical path analysis. 解釋關(guān)鍵路徑分析的優(yōu)缺點(diǎn)。
- This thesis estimate the delay of the critical path of an improved floating-point fused multiply-add (MAF) at a qualitative level, and compare it with the basic MAF implementation. 摘要針對一種改進(jìn)的浮點(diǎn)乘加器結構，對關(guān)鍵路徑的延時(shí)進(jìn)行定量的估算，并將其與傳統乘加器結構的延時(shí)進(jìn)行比較。
- In typical case, the delay of critical path is 1.38ns, power dissipation is 45.3mW, and layout area of the ALU is 0.05112mm2. The design achieves the goal of higher speed, lower power dissipation and smaller area. 三、典型條件下;所實(shí)現版圖關(guān)鍵路徑延時(shí)1.;38ns;平均功耗45
- Simulation shows that the algorithm can obtain less cost and mean path delay, it also has low time complexity. 仿真結果表明,該算法得到的多播路由樹(shù)具有較小的費用,平均路徑延遲也比較小,并且避免了其它同類(lèi)算法的高復雜性。
- Show the critical path for your project to quickly find problem tasks. 顯示項目的關(guān)鍵路徑:以快速查找有問(wèn)題的任務(wù)。
- Identifying and discuss critical path items on each job before mobilization. 動(dòng)員進(jìn)廠(chǎng)之前,辨別并討論每項工作的關(guān)鍵路徑項。
- Finally, a new test scheme to detect the crosstalk fault, based on the path delay inertia, for interconnection lines in SoC is proposed. 最后，我們提出一個(gè)利用路徑延遲慣性原理，來(lái)測試系統電路連線(xiàn)之串音障礙的新測試方法。
- On our most projects Critical Path Method( CPM) is used for scheduling. 在我們的大多數工程項目中都采用“統籌法”（關(guān)鍵路線(xiàn)方法，簡(jiǎn)稱(chēng)CPM）排計劃。
- Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. 使用完全同步設計。異步設計對路徑延遲非常敏感,因此不很可靠。異步電路的一個(gè)例子是使用組合反饋的。
- This produces a maximum path delay, which is the delay between two DTEs of 400 meters, plus the repeater delay of one repeater instead of four repeaters. 這樣就產(chǎn)生了一個(gè)最大路徑遲延，也就是兩個(gè)DTE之間的400米遲延，另外一個(gè)中繼器的遲延取代了四個(gè)中繼器的遲延。
- The critical path method was originally developed to solve scheduling problems in an industrial setting. 關(guān)鍵路線(xiàn)方法最初的發(fā)展是為了解決一項工業(yè)安裝的安排問(wèn)題。
- The key is whether you are sticking to the "critical path" when you organize your time, work space, and goals. 關(guān)鍵是當你安排自己的時(shí)間、工作范圍以及工作目標時(shí)，你是否堅定不移地走在一條“至關(guān)重要的道路”上。
- The key is whether you are sticking to the critical path when you organize your time,work space,and goals. 關(guān)鍵是當你安排自己的時(shí)間、工作范圍以及工作目標時(shí)，你是否堅定不移地走在一條“至關(guān)重要的道路”上。
- Use fully synchronous design. Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. 使用完全同步設計。異步設計對路徑延遲非常敏感,因此不很可靠。異步電路的一個(gè)例子是使用組合反饋的SR閉鎖。
- To delivery, and as a consequence puts test activities unnecessarily on the critical path of the project. 交付而完成測試準備,并且作為將不必要的測試活動(dòng)放在項目的關(guān)鍵路徑上的結果。
- MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%. 對MCNC標準單元測試電路中組合和時(shí)序電路的實(shí)驗結果顯示;電路經(jīng)過(guò)時(shí)延驅動(dòng)優(yōu)化布局后的最大路徑時(shí)延最多減少了31%25.
- Follow-up the critical path of establish of the overall long and short term goals, objectives and priorities needs. 跟進(jìn)所有短期和長(cháng)期進(jìn)度表以滿(mǎn)足工作目標和需要。
- This article discusses how to generate robust tests for path delay faults by improving the matured test generation algorithm for stuck at faults, according to the characteristics of path delay faults. 探討如何利用針對固定型故障測試產(chǎn)生的比較成熟的算法，結合時(shí)滯故障的特點(diǎn)，進(jìn)行路徑時(shí)滯故障的強健測試產(chǎn)生。
