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- PCI總線(xiàn)接口PCI bus interface
- PCI總線(xiàn)接口設備PCI bus interface device
- PCI總線(xiàn)接口設計中的幾點(diǎn)體會(huì )Review over the interface design of the PCI-bus card
- 接口interface (port)
- 高性?xún)r(jià)比PCI總線(xiàn)接口電路的設計Design for PCI bus-interface circuit with high ratio of performance and price
- PCI總線(xiàn)接口的CPLD設計Design of PCI Interface by Using CPLD
- 有諷刺意義的是,具有PCI總線(xiàn)的服務(wù)器擁有132兆字節/秒或1千兆位/秒的原始I/O吞吐能力。Ironically, servers with PCI buses are capable of raw I/O throughput of 132M byte/sec, or 1.05G bit/sec.
- 后端總線(xiàn)邏輯。訪(fǎng)問(wèn)內部統一二級處理器緩存的后端總線(xiàn)接口邏輯。BBL Back-side Bus Logic. Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
- 文中具體針對PCI總線(xiàn)的數據采集卡驅動(dòng)程序通過(guò)VC和WinDriver的利用提出了中斷的方法。Aimed at the driver of PCI bus Data sampling card,the thesis concretely advances methods of interruption in virtue of the application of VC and WinDriver.
- 總線(xiàn)接口bus interface
- PCI總線(xiàn)PCI bus
- C-PCI總線(xiàn)C-PCI bus
- 總線(xiàn)接口仿真bus interface emulation
- CAN總線(xiàn)接口CAN bus interface
- PCI總線(xiàn)協(xié)議PCI bus - protocol
- ⅡC總線(xiàn)接口IIC bus interface
- PCI總線(xiàn)從模塊PCI bus target
- SM總線(xiàn)接口SMBus interface
- PCI總線(xiàn)控制技術(shù)PCI bus control technique
- SPI總線(xiàn)接口SPI bus interface