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- 異步FIFO的FPGA實(shí)現Asynchronous FIFO Implementation Using FPGA
- 基于FPGA異步FIFO的研究與實(shí)現Research and Implementation of Asynchronous FIFO Based on FPGA
- 一款低功耗異步FIFO的設計與實(shí)現Design and Realization of a Low Power Asynchronous FIFO
- LMS算法的FPGA實(shí)現是自適應天線(xiàn)陣用于實(shí)踐的關(guān)鍵之一。FPGA-based implementation of LMS algorithm is one of the key techniques in the application of adaptive array antennas.
- 實(shí)現to achieve
- 異步FIFOasynchronous FIFO
- 基于金字塔結構編碼的8點(diǎn)離散小波變換及其逆變換的FPGA實(shí)現研究FPGA Implementation Research on 8 Samples DWT and IDWT of Pyramidal Structural Data Coding
- 基于DSP和FIFO的多路高速數據采集系統在PFN中的應用The Application of a Multi-channel High Speed Data Acquisition System Based on DSP Plus FIFO in PFN
- 在而試過(guò)程中，經(jīng)常被問(wèn)及的問(wèn)題之一就是如何計算一個(gè)FIFO的深度。One of the most common questions in interviews is how to calculate the depth of a FIFO.
- 基于FPGA的異步FIFO設計Asynchronous FIFO Design Based on FPGA
- 異步FIFO中存儲單元的分析設計Analysis and Design of Memory Cell of Asynchronous FIFO
- 混沌跳頻序列發(fā)生器的FPGA實(shí)現FPGA Realization of a Chaotic FH Sequence Generator
- 系統處理的是連續視頻信號，數據量大，采樣頻率高，本文采用了一種利用FIFO的幀中斯管理方法來(lái)解決視頻信號的采集問(wèn)題。The sampling rate of continuous video data processed by the system is high ,so we use a method by the use of FIFO frame buffer to capture the video.
- 異步FIFO在實(shí)時(shí)圖像匹配處理機中的應用Asynchronous FIFO and its application in real-time image matching system
- 根據該方案,使用FPGA實(shí)現了基于CORDIC算法的數字檢波器。On the basis of this,we propose the design scheme of digital detector based on CORDIC algorithm.
- 讀寫(xiě)數據寬度不同的異步FIFO設計Asynchronous FIFO Design with Different Data Width between Reading and Writing
- 語(yǔ)言進(jìn)行描述?；诜植际剿惴ǖ母唠AFIR濾波器及其FPGA實(shí)現High Order FIR Filter Based on Distributed Arithmetic and Its FPGA
- 本文從實(shí)際應用出發(fā),研究了橢圓曲線(xiàn)密碼體制算法的FPGA的實(shí)現;In this paper, we study the implementation of the ECC algorithm by the FPGA from practical aspect.
- IS-95碼分多址系統上行信道接收機捕獲單元的設計及FPGA實(shí)現The Design and FPGA Realization of the Capture Unit in Uplink Channel Receiver of IS 95 CDMA Cellular System
- 傳統的異步FIFO設計采用同步讀寫(xiě)地址后比較產(chǎn)生空滿(mǎn)標志的方法,面積大、工作頻率低。Traditional FIFO design often synchronizes write/read address first,then compares them to generate empty/full signals.
