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- The parallel loading of the flip-flop can be synchronous (i.e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register. 觸發(fā)器的并行加載可以是同步的（即在時(shí)鐘脈沖到達時(shí)發(fā)生）或異步的（不依賴(lài)于時(shí)鐘），這取決于移位寄存器的設計。
- The invention relates to a method and device for generating synchronous clock signals for writing operation in disk drive. 本發(fā)明涉及在磁盤(pán)驅動(dòng)器中產(chǎn)生用于寫(xiě)操作的同步時(shí)鐘信號的方法和裝置。
- In binary synchronous communication, the use of clock pulses to control synchron ization of data and control characters. 在二進(jìn)制位同步通信中,使用時(shí)鐘脈沖來(lái)控制數據和控制字符的同步。
- Trigger control circuit from complex programmable logic device (CPLD), ICL7135CN, the clock pulse circuit and optocoupler inverter constituted. 觸發(fā)控制電路由復雜可編程邏輯器件（CPLD）,ICL7135CN,時(shí)鐘脈沖電路、反相器和光耦構成。
- Design and Realization of Embedded Synchronization Clock System. 嵌入式同步時(shí)鐘系統的設計與實(shí)現。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一個(gè)高->低時(shí)鐘跳變時(shí)，（或者在最后一個(gè)時(shí)鐘脈沖的下降沿之后）主機將時(shí)鐘拉低，鍵盤(pán)/鼠標不必重新傳輸任何數據。
- DDR SDRAM is a high speed and largecapacity memory,but because of the need of synchronous clock and the characteristic that it is controlled by control command,there must be a controller between the system and DDR SDRAM. DDR SDRAM是一種大容量,高速度的同步動(dòng)態(tài)存儲器,但是由于其對同步性的要求以及需要由控制字來(lái)控制的特點(diǎn)使得他與系統之間必須有一個(gè)接口來(lái)實(shí)現時(shí)鐘同步和對DDR SDRAM進(jìn)行控制。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the last clock pulse, the keyboard/ mouse does not need to retransmit any data. 如果在第一個(gè)高->時(shí)鐘跳變時(shí)，（者在最后一個(gè)時(shí)鐘脈沖的下降沿之后）機將時(shí)鐘拉低，鍵盤(pán)/標不必重新傳輸任何數據。
- If the host pulls clock low before the first high-to-low clock transition, or after the falling edge of the a last clock pulse, the keyboard/mouse does not need to retransmit any data. 如果在第一個(gè)高->低時(shí)鐘跳變時(shí)，（或者在最后一個(gè)時(shí)鐘脈沖的下降沿之后）主機將時(shí)鐘拉低，鍵盤(pán)/鼠標不必重新傳輸任何數據。
- Note that a set of lights attached to O1, O2, O3 would display the numbers of full clock pulses which had been completed, in binary (modulo 8), from the first pulse. 注意，一組接在O1,O2,O3上的燈泡將以二進(jìn)制（模8）形式顯示第一個(gè)脈沖以來(lái)已完成的完整時(shí)鐘脈沖數。
- A microprocessor designer may decide to make all instructions last five clock pulses. 微處理機設計人員可以決定使所有的指令持續五個(gè)時(shí)鐘脈沖。
- Programmable output clock pulse width 輸出脈沖寬度可編程
- suppressed clock pulse duration modulation 壓縮時(shí)鐘脈沖寬度調制
- Summary of the Underwater Ranging Using Synchronous Clock 同步鐘式水下測距綜述
- multiphase clock pulse generator 多相時(shí)鐘脈沖發(fā)生器
- Research of Multimode Digital Synchronous Clock Technology 多模式數字同步時(shí)鐘產(chǎn)生技術(shù)研究
- An unwanted false electronic pulse. 一種不希望有的假電子脈沖。
- To get the current temperature, you must write 35 fixed bytes into the port register.The sensor expects 16 clock pulses on the SCK line while the SS# is low. 為了取得當前溫度;你必須寫(xiě)35個(gè)固定的字節到端口寄存器.;當ss低的時(shí)候，該傳感器預計16個(gè)時(shí)鐘脈沖在串行時(shí)鐘線(xiàn)。
- An online delay?evaluation approach, namely average delay window(ADW) is introduced for networked control systems, which can characterize the time delays without any synchronized clock in the network and prior assumptions about time delays. 從網(wǎng)絡(luò )控制系統的實(shí)際應用出發(fā),在不附加網(wǎng)絡(luò )同步時(shí)鐘和對時(shí)延特征的離線(xiàn)假設下,運用通訊技術(shù)中的網(wǎng)絡(luò )協(xié)議對網(wǎng)絡(luò )時(shí)延進(jìn)行在線(xiàn)估計;
- I didn't wake up until I heard the alarm clock. 直到聽(tīng)到鬧鐘的鈴聲我才醒來(lái)。
