Interconnection delay has become a dominant factor in IC design. 互連線(xiàn)時(shí)延是集成電路設計中非常重要的影響因素。
The instance results showed that the delay was well compensated, the stability and the speediness were guaranteed. 仿真結果表明，該算法的時(shí)延補償性能良好，保證了控制的快速性和穩定性。
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