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- A combinational logic element having at least one input channel. 一種至少有一個(gè)輸入通道的組合邏輯元件。
- Because of the decentralization,a large-scale logic array and ASIC digital circuit can realize the CMAC controller easily. 由于采用分散CMAC結構，簡(jiǎn)化了控制器實(shí)現的復雜度，易于采用大規?？删幊虜底诌壿嬯嚵泻虯SIC數字電路予以硬件實(shí)現。
- A clock Network is combinational logic between a clock source and the registers in the transitive fanout of the source. 時(shí)鐘網(wǎng)絡(luò )：網(wǎng)絡(luò )是一個(gè)時(shí)鐘之間的時(shí)鐘源和源寄存器傳遞扇組合邏輯。
- Field programmable logic array, FPGA, can reduce the NRE cost, design risk Time-to-Market and maintenance cost of electronic system.So FPGA is widely used in electronic systems. 現場(chǎng)可編程門(mén)陣列（FPGA）能夠減少電子系統的開(kāi)發(fā)風(fēng)險和開(kāi)發(fā)成本，縮短上市時(shí)間，降低維護升級成本，故廣泛地應用在電子系統中。
- The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper. 介紹了以Java 2標準中的Applet技術(shù)開(kāi)發(fā)組合邏輯電路網(wǎng)絡(luò )仿真實(shí)驗平臺的原理.
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA). 為了有效提高組合邏輯電路進(jìn)化設計的速度和效率，提出了一種基于博弈遺傳算法的電路進(jìn)化設計算法。
- Multiplexer is a kind of combinational logic circuit, which can be selected an in-put datum among several data and sent it to out-put port. 數據選擇器是一種能從多個(gè)輸入數據中有選擇地將一個(gè)輸入數據送到輸出端的組合邏輯電路。
- In this paper a method of a combinational logic B/BCD converosin Jor any BCD code is investigated, And some example are given to illustra-te the use of the method. 本文以幾種常用的BCD碼為例;深入研究任意BCD碼的B/BCD轉換的組合邏輯變換網(wǎng)絡(luò ).
- Network configuration of separated Crossbar employs the SEED devices as high speed optical modulators and the FET SEED device integrated on a single GaAs chip as optical logic array. 該體系結構中可采用自電光效應（SEED）器件作為高速光調制器，采用在單塊GaAs基片上集成的場(chǎng)效應晶體管－自電光效應器件（FET－SEED）作為邏輯光開(kāi)關(guān)器件。
- FPGA, Field programmable logic array, can reduce the NRE cost, design risk, Time-to-Market and maintenance cost of electronic system.Therefore, FPGA is widely used in electronic systems. 現場(chǎng)可編程門(mén)陣列（FPGA）能夠減少電子系統的開(kāi)發(fā)風(fēng)險和開(kāi)發(fā)成本，縮短 上市時(shí)間，降低維護升級成本，故廣泛地應用在電子系統中。
- By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis. 提出一種通過(guò)將RTL描述劃分為時(shí)序邏輯與組合邏輯后 ;重用控制器綜合中的組合邏輯綜合和時(shí)序邏輯綜合實(shí)現 RTL綜合的方法 .;此方法有效地利用了已有的成熟技術(shù);為縮短 RTL綜合的開(kāi)發(fā)時(shí)間提供了一種有效途徑
- In designing auto-control devices including computer, apart from the combinational logic design, the now fairly popular method which attracts daily increasing attention is the microprogramming. 設計包括計算機在內的自動(dòng)控制裝置,除采用組合邏輯設計方法外,目前比較流行、且愈來(lái)愈為人們重視的方法,是微程序設計方法。
- To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm (GGA).In GGA, each output of the circuit was regarded as a player. 摘要為了有效提高組合邏輯電路進(jìn)化設計的速度和效率，提出了一種基于博弈遺傳算法的電路進(jìn)化設計算法。
- FPLA Field Programmable Logic Array 現場(chǎng)可編程邏輯陣列
- autonomous testable programmable logic array 獨立可測的可編程序邏輯陣列
- bipolar programmable logic array 雙極型可編程邏輯陣列
- Computer aided logical design(CALD) software design rapidly and exactly combinational logical and sequential logical circuits. 該軟件可以快速、準確、可靠地設計出多輸入多輸出液控邏輯回路，設計結果可以達到最優(yōu)。
- rewritable programmable logic array 可重寫(xiě)可編程邏輯陣列
- iterate logic array testing method 迭代邏輯陣列測試法
- At this point your logic is at fault. 在這一點(diǎn)上你的推理是錯誤的。
