Using a modern development technology of DSP(DSP Builder) implementation for example,the FPGA design,which was verified in the digital signal process circuit of an 16-order FIR filter was mainly presented.
英
美
- 提出了一種采用DSP Builder實(shí)現有限沖激響應濾波器的設計方案,并以一個(gè)16階低通FIR數字濾波器的實(shí)現為例,設計并完成軟硬件仿真與驗證。 結果表明,該方法簡(jiǎn)單易行,能滿(mǎn)足設計要求。
