To verify the model, a test circuit has been designed to simulate parasitical latch-up paths in CMOS devices and relevant parameters are reported.是什么意思_To verify the model, a test circuit has been designed to simulate parasitical latch-up paths in CMOS devices and relevant parameters are reported.在線(xiàn)翻譯_英語(yǔ)_讀音_用法_例句