This paper provides the design method of a high speed fixed point multiplier. It employs Modified Booth Arithmetic(MBA), Wallace-Tree, 4:2 Compressor, pseudo 4:2 compressor and the Suqare Root Carry-Select Adder.
英
美
- 文章系統地研究了符號定點(diǎn)高速乘法器的實(shí)現算法和結構,采用了修正布斯算法,華萊士壓縮樹(shù),4:2壓縮器,偽4:2壓縮器以及平方根求和結構。