This paper discusses the theory of AES algorithm,and describes its process and structure with Verilog HDL. Based on the structure,it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits.是什么意思_This paper discusses the theory of AES algorithm,and describes its process and structure with Verilog HDL. Based on the structure,it completes the FPGA design of AES encryption and decryption algorithm when block length is 128bits.在線(xiàn)翻譯_英語(yǔ)_讀音_用法_例句