This architecture is developed from aparallel VLSI architecture for FS. Moreover, function modules of 2SS motionestimation are set off. And they are designed, implemented and simulated with VerilogHDL, ISE and Modelsim on Spartan-IIE XC2S300e FPGA chips.

 
  • 本文對已有的用于全搜索算法實(shí)現的VLSI結構進(jìn)行了改進(jìn),設計了符合二步搜索算法要求的FPGA實(shí)現結構,并在對其理論分析之后,對實(shí)現該算法的運動(dòng)估計模塊進(jìn)行了功能模塊的劃分,并運用Verilog HDL硬件描述語(yǔ)言、ISE及Modelsim開(kāi)發(fā)工具在Spartan-IIE XC2S300e FPGA芯片上完成了對各功能模塊的設計、實(shí)現與時(shí)序仿真。
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