These building blocks in clude gated D flip-lops for r educed p ower consumption,current DAC with minimized spikes,pixel cell im mune from device and process variations and large output swing.

 
  • 這些模塊包括用于降低功耗的帶門(mén)D觸發(fā)器,具有最小尖刺噪聲的電流模式DAC,所設計的象素單元對器件和工藝的差異不敏感,并具有較大的輸出范圍。
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