The objective of this research is the former-end hardware design for the 64-bit RISC(Reduced Instruction Set Cpomputer)CPU core and the implementation and verification of the design on FPGA(Field Programmable Gate Array).是什么意思_The objective of this research is the former-end hardware design for the 64-bit RISC(Reduced Instruction Set Cpomputer)CPU core and the implementation and verification of the design on FPGA(Field Programmable Gate Array).在線(xiàn)翻譯_英語(yǔ)_讀音_用法_例句