The layout design of the proposed pipelined ADC has been finished and the test chip is being implemented.

 
  • 設計的模數轉換器在0.;6um工藝下全部電路運行功耗僅為49mW;比同類(lèi)電路的平均功耗要低13%25;實(shí)現了低功耗的設計。
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