The field programmable gate array(FPGA) simulation shows that compared to the multiplier with Radix?8 Booth algorithm,the speed of this multiplier is increased by 11% and its hardware resource is reduced by 3%.

 
  • 經(jīng)現場(chǎng)可編程邏輯器件仿真驗證表明;與采用Radix-8 Booth算法的乘法器相比;該乘法器速度提高了11%25;硬件資源減少了3%25.
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