The RTL (Register Transfer Level)design is accomplished by Veirlog hardware description language, and synthesized with the standard cell library of SMIC 0.18um. The working frequency of the adaptive filter is 50MHz.

 
  • 本設計采用Verilog 硬件描述語(yǔ)言完成系統的RTL(Register Transfer Level)級設計;選用SMIC 0.;18um 標準單元庫完成邏輯綜合;系統工作速度為50MHz。
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