On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.是什么意思_On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.在線(xiàn)翻譯_英語(yǔ)_讀音_用法_例句