Finally,the interface between microprocessor and RSA,or between RSA and EEPROM is implemented to realize the whole system function. The design of IIC part is depicted with Verilog HDL. By Verilog-XL tools,behavior simulation is achieved.
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- 對于RSA模塊和外界及安全芯片存儲器EEPROM的通訊接口IIC模塊的軟核設計，劃分了具體的模塊，針對每個(gè)模塊使用Verilog HDL 語(yǔ)言進(jìn)行描述，通過(guò)Verilog-XL完成了軟件平臺上的行為級仿真，實(shí)現了系統的整體協(xié)同工作。
