Compared with a two stage Vdd and Vth voltage assignment with gate sizing algorithm in [13], our algorithm also consume 4.2% and 9.7% less average total power than it.

 
  • 和一個(gè)分成兩階段的演算法作比較,我們在中活性與低活性里,也分別可以比他們的演算法減少4.;2%25和9
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