Because equivalence checking is designed to check the correctness of automatic synthesis from RTL to netlist, correctness is also the key point, which is concerned in this paper.

 
  • 設計驗證系統的初衷是驗證給定設計從RTL級到網(wǎng)表級自動(dòng)綜合后電路的正確性,所以綜合引擎本身的正確性是本文首要關(guān)注的問(wèn)題。
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