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- 乘法器采用改進(jìn)的Booth算法,簡(jiǎn)化了部分積符號擴展,使用Wallace樹(shù)結構和4-2壓縮器對部分積歸約。This multiplier used modified Booth Algorithm, Wallace tree and 4- 2 compressor.
- 模擬驗證表明,與采用傳統Wallace樹(shù)結構和改進(jìn)Booth二階算法的乘法器相比,該乘法器的乘法延時(shí)減少了23%,功耗降低了17%,面積減少了20%.Compared to the conventional multiplier with modified Booth algorithm for radix-4 and Wallace tree architecture,the proposed techniques employed in the multiplier reduces 17%25 of the power dissipation and 23%25 of the multiplication time,and the area of multiplier is reduced by 20%25.
- 改進(jìn)to improve
- 對于SA-DCT,采用Booth算法對DCT系數編碼,用可編程處理器的概念實(shí)現不同長(cháng)度DCT的變換,同時(shí)提出了一種新穎的轉置寄存器陣列實(shí)現所必需的轉置操作,整個(gè)結構面積為12500門(mén),最大功耗為2.54mW。Second, for the design of SA-DCT, booth encoding is introduced for coefficients of DCT, and the design concept of programmable processor is adopted to computing various-length DCT while a novel transposed register array is proposed to implement the transpose operation necessary for SA-DCT. The proposed SA-DCT core costs about 12500 gates with the maximum power consumption of 2.54mW.
- 改進(jìn)的modified
- 改進(jìn)措施corrective measure
- Booth算法Booth algorithm
- 高基Booth算法high radix Booth algorithm
- Booth編碼算法optimal Booth coder
- 改進(jìn)Booth編碼Modified Booth encoder
- 冗余Booth算法redundant Booth algorithm
- 改進(jìn)的Booth編碼improved Booth encoding
- 棋類(lèi)博弈算法的改進(jìn)Improvement on Algorithm of Chess Game
- 改進(jìn)算法improved algorithm
- booth’S乘算法與基2{?,0,1}記數制系統BOOTH'S ALGORITHM AND RADIX TWO {(1|-),0,1} NUMERATION SYSTEM
- 改進(jìn)型booth華萊士樹(shù)的低功耗、高速并行乘法器的設計Low Power and High-Speed Parallel Multiplier Design Using Modified Booth Wallace Tree
- 算法改進(jìn)algorithm improvement
- 策略改進(jìn)算法policy improvement algorithm
- 改進(jìn)BP算法improved BP algorithm
- 改進(jìn)GS算法improved GS algorithm
